Integrated circuits (IC's) are prone to damage and failure from an electro-static-discharge (ESD). ESD failures may occur in the factory and contribute to lower yields. Various ESD-protection structures have been placed near input, output, or bi-directional I/O pins of ICs. Many of these protection structures use passive components such as series resistors, diodes, and thick-oxide transistors. Other ESD structures use an active transistor to safely shunt ESD current.
As manufacturing ability improves and device sizes shrink, lower voltages are applied to transistors during normal operation. These smaller transistors are much more susceptible to over-voltage failure but can operate with a lower power-supply voltage, thus consuming less power and producing less heat.
Such smaller transistors are often placed in an internal “core” of an IC, while larger transistors with gate lengths that are above the minimum are placed around the core in the periphery. ESD-protection structures are placed in the periphery using these larger transistors.
Thinner gate oxides of the core transistors can be shorted, and substrate junctions melted by relatively small capacitivly-coupled currents applied to the tiny core devices. Static charges from a person or machinery can produce such damaging currents that are only partially blocked by the input-protection circuits in the periphery.
FIG. 1 shows a chip with several ESD-protection clamps. Low-voltage core circuitry 20 contains core transistors 22, 24, which have a small channel length and can be damaged by relatively low voltages. Low-voltage core circuitry 20 receives a power supply voltage VDD, such as 3 volts, 1.8 volts, 1.2 volts, or some other value. There may be thousands of core transistors in low-voltage core circuitry 20.
Protection from ESD pulses may be provided on each I/O pad, and by power clamp 16. Power clamp 16 is coupled between VDD and ground (VSS), and shunts current from an ESD pulse between the power rails.
Some cross-coupling may occur between different pads and low-voltage core circuitry 20, such as through substrates and capacitances. An ESD pulse applied to one I/O pad 30 may be coupled into low-voltage core circuitry 20 by this cross-coupling, causing damage to transistors 22, 24 in low-voltage core circuitry 20. Power clamp 16 may shunt enough current from the ESD pulse to reduce such cross-coupling to prevent damage. ESD pulses applied to I/O pins may still couple into low-voltage core circuitry 20, such as through power lines, but power clamp 16 may then be activated to reduce potential damage. Power clamp 16 may also turn on for other ESD pulses such as those applied to I/O pins, when the ESD pulse is shunted through a diode in the I/O pin's ESD-protection structure to the internal VDD rail, causing an indirect VDD-to-VSS ESD pulse. For example, an ESD pulse applied to I/O pad 30 may cause ESD protection device 32 to turn on to conduct to VDD.
Each I/O pad 30 may be outfitted with several ESD protection devices 32, 34, 36, 38 to protect against various possibilities. ESD protection device 38 turns on for a positive ESD pulse applied between I/O pad 30 and ground, while ESD protection device 36 turns on for a negative ESD pulse applied between I/O pad 30 and ground. Likewise, ESD protection device 32 turns on for a positive ESD pulse applied between I/O pad 30 and VDD, while ESD protection device 34 turns on for a negative ESD pulse applied between I/O pad 30 and VDD. Power clamp 16 may also turn on in some situations.
FIG. 2 is a graph of I-V characteristics of high-voltage transistors used in ESD protection devices and of low-voltage transistors used in low-voltage core circuitry 20. As a pulse such as an ESD pulse is applied to a low-voltage transistor such as is used in low-voltage core circuitry 20, the low-voltage transistor is turned off so the current is low as the voltage rises from the origin, as shown for curve 90.
Once the voltage is above the avalanche or punch-through breakdown voltage VTL, at current ITL, drain-to-source breakdown occurs (punch-through or avalanche breakdown of the parasitic NPN transistor in an n-channel transistor). The current then increases dramatically as the voltage is reduced (snaps back) as current flow continues to increase until the current reached the holding current IHL at the holding voltage, VHL. This holding voltage VHL must be above the power-supply voltage VDD to prevent latch-up.
As more current is applied to the transistor at the holding voltage, the current rises quickly until the second threshold voltage is reached, at a high current. Then thermal breakdown occurs as portions of the transistor may melt or otherwise be permanently damaged.
Curve 92 is similar in shape to curve 90, but has higher voltage thresholds for snap-back or avalanche breakdown, since curve 92 is for high-voltage transistors that are typically used in ESD protection devices. The high-voltage transistor reached snap-back threshold voltage VTH before the high-voltage transistors break down, but after low-voltage transistors in low-voltage core circuitry 20 break down, as shown by the LV-Core Breaks vertical line. Thus high-voltage transistors are not effective in protecting low-voltage transistors in low-voltage core circuitry 20.
A low snap-back trigger voltage is needed to protect the low-voltage transistors, but a high holding voltage is needed to prevent latch-up of the low-voltage transistors to the power supply. Thus there is a design window between VDD and the snap-back trigger voltage. This design window may be relatively small and difficult to achieve. As processes shrink, VDD and breakdown voltages are also reduced, reducing the design window.
Some prior-art ESD protection structures have large-area capacitors, resistors, or transistors which are undesirable. A special ESD implant step may be added to some complementary metal-oxide-semiconductor (CMOS) processes to fortify ESD structures. Unfortunately, breakdown voltages may still be less than trigger voltages, allowing damage to occur despite the ESD implant.
Leakage may be a problem for some structures, especially diode or diode-triggered structures. Leakage from p-n junctions is sometimes a problem with some ESD protection devices. Trigger voltages may be larger than breakdown voltages, allowing damage to occur before devices are triggered.
What is desired is an electro-static-discharge (ESD) protection circuit with a low snap-back trigger voltage and a high holding voltage. An ESD protection device featuring parallel paths to allow for better optimization is desirable. Using a resistor path to set the trigger voltage and a diode path to conduct a larger current and set the holding voltage is desired. A snap-back structure using an ESD implant under a drain is desired.